In the field of electronics various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design. Once the PLD has been programmed within a working system, however, it is also important to be able to debug the PLD in this real-world environment.
And although a simulation may be used to debug many aspects of a PLD, it is nearly impossible to generate a simulation that will accurately exercise all of the features of the PLD on an actual circuit board operating in a complex system. For example, a simulation may not be able to provide timing characteristics that are similar to those that will actually be experienced by the PLD in a running system; e.g., simulation timing signals may be closer or farther apart than what a PLD will actually experience in a real system.
In addition to the difficulties in generating a comprehensive simulation, circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a PLD that are only evident when the PLD is operating within a working system. Still further, it can be difficult to generate sufficiently varied test vectors to stress the PLD design to the point where most bugs are likely to be observed. For example, a PLD malfunction can result when the PLD is presented with stimuli that the designer did not expect, and therefore did not take into account during the design and simulation of the PLD. Such malfunctions are difficult to anticipate and must be debugged in the context of the complete system. Thus, simulation of an electronic design is useful, but usually cannot debug a PLD completely.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. Typically, a number of probe wires are connected manually from the logic analyzer to pins of interest on the hardware device in order to monitor signals on those pins. The logic analyzer captures and stores these signals for later viewing and debugging.
As an external logic analyzer may not always be optimal, embedding a logic analyzer within the hardware device is another technique used. For example, U.S. Pat. No. 6,182,247 entitled “Embedded Logic Analyzer for a Programmable Logic Device” discloses such a technique, and U.S. Pat. Nos. 6,286,114 and 6,247,147 disclose enhancements. In addition, viewing internal nodes in a device may be performed as disclosed in U.S. Pat. Ser. No. 6,754,862. Embedding a logic analyzer into a design is also a technique used in the product “ChipScope ILA” available from Xilinx Inc., of San Jose, California. The product “ChipScope Pro” also available from Xilinx uses logic cores built directly into a PLD to allow a user to access internal signals and nodes for debugging.
As useful as these techniques are in debugging a PLD, there is room for improvement. For example, as described in U.S. Pat. No. 6,286,114, a user controls a single embedded logic analyzer through a JTAG port. While such a technique is extremely useful, in many situations it would be desirable to have more than one internal debugging tool have access to the JTAG port, while still maintaining the benefits of a direct interface. In other words, it would be desirable for the user to be able to communicate with, and control, any number of internal logic analyzers, other debugging tools, or other applications through the JTAG port or a suitable serial interface.
For example, a PLD may use two different clock domains (or more) such as a 100 MHz and a 50 MHz clock. With two different clock speeds, a single embedded logic analyzer might not be able to capture debugging data from within the different clock domains. It would be useful to have two or more logic analyzers, each running at a different clock speed and still communicating to the user via a single, serial interface. The user may also wish to capture data from within different parts of the PLD using two or more different trigger conditions. Again, having more than one logic analyzer would be very useful.
The ChipScope product available from Xilinx, Inc. does provide the ability to have multiple logic analyzers within a PLD. It is believed, though, that these logic analyzers must be placed in series within the PLD which has disadvantages. For example, a user or software application desiring to access one of the logic analyzers using the ChipScope product needs to know about all of the internal logic analyzers and where the particular analyzer sits in the series chain. Requiring a user or software tool to be aware of all internal debugging tools and to coordinate amongst them can be confusing and inefficient.
It would be desirable to allow the user of an EDA tool to communicate with, and control, any number of embedded logic analyzers, debugging tools, or other internal applications that are within a PLD. Further, it would be desirable for the user to be able to control such a tool irrespective of any other internal tool, and to be able to do so via any single JTAG port or other serial interface.